Example embodiments relate to semiconductor devices and, more particularly, to semiconductor devices and methods for repairing the same.
Generally, semiconductor memory devices are classified into volatile memory devices and non-volatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted, while non-volatile memory devices retain their stored data even when their power supplies are interrupted.
Flash memory devices are non-volatile memory devices and may be classified into NOR-type flash memory devices (hereinafter referred to as “NOR flash memories”) and NAND-type flash memory devices (hereinafter referred to as “NAND flash memories”). A NAND flash memory is configured to control a string of memory cells at the same time, while a NOR flash memory is configured to control memory cells independently.
A typical NOR flash memory includes a cell array region, which may include a main cell array region and a redundancy cell array region formed at one side or both sides of the main cell array region. The main cell array region includes global bitlines and local bitlines that are connected to the global bitlines. The redundancy cell array region includes redundancy bitlines and local redundancy bitlines that are connected to the redundancy bitlines.
The memory cell array region may include a number of memory cells disposed in a matrix of wordlines and local bitlines. Even if only one of the memory cells is defective, a NOR flash memory is generally not capable of performing operations. As integration density of semiconductor devices increases, the likelihood that a memory cell of a NOR flash memory is defective increases. A defective memory cell (hereinafter referred to as “fail cell”) is a major cause of yield reduction in a NOR flash memory. Thus, if a fail cell is generated in a NOR flash memory, a bitline connected to the fail cell must be replaced with a redundancy bitline to compensate for a defect. For example, if an address is provided to select a fail cell, a redundancy bitline connected to a redundancy cell may be replaced with a global bitline connected to the fail cell to enable a NOR flash memory to operate normally.
That is, if a fail cell is generated in the main cell array region, a global bitline electrically connected to the fail cell is replaced with the redundancy bitline to be repaired. For this reason, repair technology for replacing a bitline connected to a fail cell with a redundancy bitline connected to a redundancy cell is important.